In a typical memory system of a computer system, a memory controller facilitates the access of one or more memory modules in the computer system. Each memory module may include one or more memories that are referred to as ranks. As demand for lower power consumption of computer systems increases, power management of the memory modules and/or the ranks in the memory modules is needed. Power management of memories is even more imperative as demand for larger memories is increasing. For example, a memory of 4 Giga byte (Gb) size with 12 Dual-Inline Memory Modules (DIMMs) operating via a Double Data Rate (DDR) 3 I/O interface consumes about 28% of the total computer system power consumption when the memory is operating at its maximum bandwidth. A larger memory of 8 Gb size with 16 DIMMs on the same I/O interface consumes about 40% of the total computer system power consumption. The above trend becomes alarming for larger memories and faster I/O interfaces such as DDR 4 I/O interfaces.
Memory controllers manage power consumption of the memory modules and/or ranks mainly by disabling the clock signal to the memory modules that are identified as idle or inactive. A disabled clock signal reduces the dynamic power component of the total power consumption of the memory modules because logic gates of the memory modules that switch in response to the toggling of the clock signal no longer switch. The term idle or inactive herein refers to a period of time during which no data is read or written to the memory modules.
The amount of power consumption saved by disabling the clock signal depends on how long a memory (module(s) or independent ranks) remains in an idle state. Depending on how long a memory remains in the idle state, the memory controller may place the memory in one of several power states. Each power state has an associated latency time (also called the exit latency time) representing the time it takes to bring the memory from an idle state to a live state. Live or active state refers herein to a state of a memory (module(s) or independent ranks) in which the memory is receiving read and/or write commands from the memory controller.
If the memory controller determines that a memory (module(s) or independent ranks) will remain in an idle state longer than a predetermined threshold, it places the memory in a power state that has a longer latency time than another power state from among the several power states. A power state that has a longer latency time than another power state also means that it will cause the memory to take a longer time to become active. A longer latency time thus translates to lower computer performance because a user is not able to access the memory till the memory goes in active state.
The above described power management of the memory (module(s) or independent ranks) is not visible by any operating system. The operating system plays an active role in allocating memory of the memory modules including ranks for various operations/tasks. However such memory allocation does not take into account the power states of the memory (module(s) or independent ranks). Nor does the operating system know the duration the memory (module(s) or independent ranks) remains in a particular power state. During memory allocation for a current or future task, the operating system may allocate memory from a memory module having most of its ranks in idle state i.e., a lower power consumption state. Such allocation of memory may cause the entire memory module to enter an active state and lose potential power consumption savings from being in idle state because the operating system did not take into account the power state of the memory modules and/or ranks.